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Espressif Systems /ESP32-P4 /LP_SYS /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LP_ADDRHOLE_INT_ST)LP_ADDRHOLE_INT_ST 0 (IDBUS_ADDRHOLE_INT_ST)IDBUS_ADDRHOLE_INT_ST 0 (LP_CORE_AHB_TIMEOUT_INT_ST)LP_CORE_AHB_TIMEOUT_INT_ST 0 (LP_CORE_IBUS_TIMEOUT_INT_ST)LP_CORE_IBUS_TIMEOUT_INT_ST 0 (LP_CORE_DBUS_TIMEOUT_INT_ST)LP_CORE_DBUS_TIMEOUT_INT_ST 0 (ETM_TASK_ULP_INT_ST)ETM_TASK_ULP_INT_ST 0 (SLOW_CLK_TICK_INT_ST)SLOW_CLK_TICK_INT_ST

Description

masked interrupt register

Fields

LP_ADDRHOLE_INT_ST

the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave)
IDBUS_ADDRHOLE_INT_ST

the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
LP_CORE_AHB_TIMEOUT_INT_ST

the masked interrupt status of lp core ahb bus timeout
LP_CORE_IBUS_TIMEOUT_INT_ST

the masked interrupt status of lp core ibus timeout
LP_CORE_DBUS_TIMEOUT_INT_ST

the masked interrupt status of lp core dbus timeout
ETM_TASK_ULP_INT_ST

the masked interrupt status of etm task ulp
SLOW_CLK_TICK_INT_ST

the masked interrupt status of slow_clk_tick

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data